研究内容

　専門分野を強いて指定すれば「電子回路工学」となります。その中でも
「論理回路・アナログ電子回路の設計とテスト」を専門に研究を行っています。

　過去にはAI手法を用いたアナログ電子回路・論理回路の設計自動化法に関して研究を行っていましたが、
現在は下記の内容に関する研究を主として行っています。

　　・論理ICの電気的テスト
　　・論理回路，アナログ電子回路の電気的テスト容易化設計法
　　・プリント配線板上に実現した論理回路の電気的検査
　　・論理回路の低消費電力化
　　・論理回路設計自動化

　研究成果の詳細は徳島大学理工学部のページ（こちら）にアップされていますが、
ここでは1997年以降の研究成果の概要と獲得した公的外部資金について公開します。

■最近の研究成果の概要(1997年以降分）

<2021年>
・　Yuki Ikiri, Fumiya Sako, Masaki Hashizume, Hiroyuki Yotsuyanagi, Lu Shyue-Kung, Yazaki Toru, Ikeda Yasuhiro and Uematsu Yutaka : Open Defect Detection in Assembled Circuit Boards with Built-In Relaxation Oscillators, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol.11, No.6, 931-943, 2021.
・　okumoto yuya, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Detectable Resistance Increase of Open Defects in Assembled PCBs by Quiescent Currents through Embedded Diodes, Proc. of 2021 International Conference on Electronics Packaging (ICEP), Tokyo, May 2021.

<2020年>
・　Kanda Michiya, Masaki Hashizume, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol.10, No.5, 895-907, 2020.
・　Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume and Hiroyuki Yotsuyanagi : Fault-Aware Dependability Enhancement Techniques for Flash Memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.28, No.3, 634-645, 2020
・　Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama and Shyue-Kung Lu : Recovery of Defective TSVs with A Small Number of Redundant TSVs in 3D Stacked ICs, the 21st IEEE Workshop on RTL and High Level Testing, Online, Nov. 2020.
・　Kanami Nagata, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Time Reduction of Small Delay Testing for Scan Design with Embedded TDC, the 21st IEEE Workshop on RTL and High Level Testing, Online, Nov. 2020.
・　Sako Fumiya, yuki ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yokoyama Hiroshi and Shyue-Kung Lu : Temperature Sensing with a Relaxation Oscillator in CMOS ICs, Proc. of The 35th International Technical Conference on Circuits/Systems, Computers and Communications, 141-144, Jul. 2020.

<2019年>
・　Toshiaki Satoh, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection, Proc. of The IEEE 2019 International 3D Systems Integration Conference, P4023-1-P4023-4, Sendai, Oct. 2019.
・　Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes, Proc. of The IEEE 2019 International 3D Systems Integration Conference, P4022-1-P4022-5, Sendai, Oct. 2019.
・　Shuya Kikuchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Delay Measurement under Delay Variations in Boundary Scan Circuit with Embedded TDC, Proc. 2019 IEEE International Test Conference in Asia, 169-174, Tokyo, Sep. 2019.
・　Michiya Kanda, Daisuke Yabui, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Stand-by Mode Test Method of Interconnects between Dies in 3D ICs with IEEE 1149.1 Test Circuits, Proc. of IEEE CPMT Symposium Japan 2018, 189-192, Kyoto, Nov. 2018.

<2018年>
・　Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin and Masaki Hashizume : Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories, Journal of Electronic Testing - Theory and Applications, Vol.34, No.4, 435-446, 2018.
・　ASHIKIN Fara, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung LU and Zvi ROTH : A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs, IEICE Transactions on Information and Systems, Vol.E101-D, No.8, 2053-2063, 2018.
・　Yuta Matsumoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defect Detection in SoCs by a Test Method Based on Injected Charge Volume after Test Input Application, Proc. of IEEE CPMT Symposium Japan 2018, 141-142, Kyoto, Nov. 2018.
・　Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design, Proc.of IEEE 27th Asian Test Symposium, 7-12, Hefei, Oct. 2018.
・　Ishihara Ken, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defects in 3D Stacked ICs Detected by Electrical Interconnect Testing with a Charge Injector Made of MOS Capacitors, Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), 114-117, Bangkok, Jul. 2018.
・　Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Design and Evaluation of a TDC Cell Embedded in the Boundary Scan Circuit for Delay Fault Testing of 3D ICs, Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), 110-113, Bangkok, Jul. 2018.
・　Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification, 24th IEEE International Symposium on On-Line Testing and Robust System Design, Spain, Jul. 2018.
・　Masaki Hashizume : Health Monitoring of Electronic Circuits in IoT Systems, Proc. of International Forum on Advanced Technologies 2019, 29, Taipei, Taiwan, Mar. 2018.
・　Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effect of Routing in Testing a TSV Array Using Boundary Scan Circuit with Embedded TDC, Proc. of International Forum on Advanced Technologies 2018, P1-13-1-P1-13-3, Tokushima, Japan, Mar. 2018.
・　Alia Ashikin Fara, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Proc. of International Forum on Advanced Technologies 2018, P1-12-1-P1-12-3, Tokushima, Japan, Mar. 2018.
・　Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defect Detection in 3D ICs with a Comparator of Offset Cancellation Type under Process Variation, Proc. of International Forum on Advanced Technologies 2018, P1-11-1-P1-11-3, Tokushima, Japan, Mar. 2018.
・　Miyatake Noriko, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama and Tetsuo Tada : Oscillation Frequency Estimation of Ring Oscillator for Interconnect Tests in 3D Stacked ICs, Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications, 659-662, Mar. 2018.
・　Hanna Soneda, Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Kung Shyue LU : Detectable Resistive Open Defects in 3D ICs with Electrical Interconnect Test Circuit Made of Diodes, Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications, 655-658, Mar. 2018

<2017年>
・　Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.12, 2842-2850, 2017.
・　Fara Alia Ashikin, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Journal of Telecommunication, Electronic and Computer Engineering, Vol.9, No.3-2, 49-52, 2017.
・　Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC, Journal of Telecommunication, Electronic and Computer Engineering, Vol.9, No.3-2, 39-42, 2017.
・　Zheng-Hong Cai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Modified PRPG for Test Data Reduction Using BAST Structure, Journal of Signal Processing, Vol.21, No.4, 125-128, 2017.
・　Morito Niseki, Toshinori Hosokawa, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Sequentially Untestable Fault Identification Method Based on State Cube Justification, the 18th IEEE Workshop on RTL and High Level Testing, 43-46, Taipei, Dec. 2017.
・　Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC, the 18th IEEE Workshop on RTL and High Level Testing, Taipei, Dec. 2017.
・　Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume and Hiroyuki Yotsuyanagi : Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories, Proc.of IEEE 26th Asian Test Symposium, 249-254, Taipei, Nov. 2017.
・　Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume and Shyue-Kung Lu : Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs, Proc.of IEEE 26th Asian Test Symposium, 237-242, Taipei, Nov. 2017.
・　Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defects Detected by Interconnect Testing Based on Charge Volume Injected to 3D ICs, Proc. of IEEE CPMT Symposium Japan 2017, 231-234, Kyoto, Nov. 2017.
・　Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Current Sensor Made of a Comparator of Offset Cancellation Type for Electrical Interconnect Tests of 3D ICs, Proc. of IEEE CPMT Symposium Japan 2017, 137-138, Kyoto, Nov. 2017.
・　Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Defective Level Monitor of Open Defects in 3D ICs with a Comparator of Offset Cancellation Type, 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 1-4, Cambridge, Oct. 2017.
・　Yuuya Ohama, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yoshinobu Higami and Hiroshi Takahashi : On Selection of Adjacent Lines in Test Pattern Generation for Delay Faults Considering Crosstalk Effects, Proc. of 17th International Symposium on Communications and Information Technologies, 96-100, Cairns, Sep. 2017.
・　Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Defect Level Monitor of Resistive Open Defect at Interconnects in 3D ICs by Injected Charge Volume, Proc. of 17th International Symposium on Communications and Information Technologies, 46-50, Cairns, Sep. 2017.
・　Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Capacitive Open Detection in 3D ICs with A Built-in Comparator of Offset Cancellation Type, IEEE 2017 Taiwan and Japan Conference on Circuits and Systems, Okayama, Aug. 2017.
・　Michiya Kanda, Masaki Hashizume, Akihiro Odoriba, Yohei Kakee, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Test Circuit Using A Comparator of Offset Cancel Type for Electrical Interconnect Tests of 3D Stacked ICs, Proc. of International Forum on Advanced Technologies 2017, 233-235, Hualien, Taiwan, Mar. 2017.
・　Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Test Input Vectors for Detecting Stuck-at Faults at Address and Data Buses in 3D Stacked Memory ICs, Proc. of International Forum on Advanced Technologies 2017, 127-129, Hualien, Taiwan, Mar. 2017.
・　Zheng-Hong Cai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Modified PRPG for Test Data Reduction Using BAST Structure, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 441-444, Guam, Mar. 2017.

<2016年>
・　Widiant, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu and Zvi Roth : A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs, IEICE Transactions on Information and Systems, Vol.E99-D, No.11, 2723-2733, 2016.
・　Shyue-Kung Lu, Cheng-Ju Tsai and Masaki Hashizume : Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.24, No.8, 2726-2734, 2016.
・　橋爪 正樹, 伊喜利 勇貴, 小西 朝陽, 四柳 浩之, Shyue-Kung Lu : バウンダリスキャンテスト機構を用いたはんだ接合部の電気検査法とその組込型検査回路, エレクトロニクス実装学会誌, Vol.19, No.3, 161-165, 2016年. ・　Fara Ashikin Binti Ali, Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Capacitive Open Defect Detection by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops, Proc. of the 17th IEEE Workshop on RTL and High Level Testing, 1-2-1-1-2-6, Hiroshima, Nov. 2016.
・　Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Control Circuit and Observation Conditions for Testing Multiple TSVs Using Boundary Scan Circuit with Embedded TDC, Proc. of the 17th IEEE Workshop on RTL and High Level Testing, 1-3-1-1-3-6, Hiroshima, Nov. 2016.
・　Shyue-Kung Lu, Shang-Xiu Zhong and Masaki Hashizume : Enhancement of Flash MemoriesAdaptive ECC Techniques for Yield and Reliability, Proc. of 2016 IEEE 25th Asian Test Symposium, 287-292, Hiroshima, Nov. 2016.
・　Ali Ashikin Binti Fara, Masaki Hashizume, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testability for Resistive Open Defects by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops, Proc. of IEEE CPMT Symposium Japan 2016, 137-138, Kyoto, Nov. 2016.
・　Kouhei Ohtani, Masaki Hashizume, Daisuke Suga, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Power Supply Circuit for Interconnect Tests Based on Injected Charge Volume of 3D IC, Proc. of IEEE CPMT Symposium Japan 2016, 139-140, Kyoto, Nov. 2016.
・　Masaki Hashizume, Akihiro Odoriba, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Defective Level Monitor of Resistive Open Defects in 3D ICs with Logic Gates, Proc. of IEEE CPMT Symposium Japan 2016, 99-102, Kyoto, Nov. 2016.
・　Fara Binti Ali Ashikin, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Proc. of International Design and Concurrent Engineering Conference 2016, Langkawi, Sep. 2016.
・　Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokiyama, Tetsuo Tada and Shyue-Kung Lu : Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC, Proc. of International Design and Concurrent Engineering Conference 2016, Langkawi, Sep. 2016.
・　Kouhei Ohtani, Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Test Circuit for Injected Charge Tests of Open Defects in CMOS ICs, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016, 291-294, Okinawa, Jul. 2016.
・　Masashi Okamoto, Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : A Built-in Test Circuit to Monitor Changing Process of Resistive Open Defects in 3D ICs, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016, 295-298, Okinawa, Jul. 2016.
・　Takumi Miyabe, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : A Built-in Electrical Test Circuit for Detecting Open Leads in Assembled PCB Circuits with RC Integrator, Proceedings of International Conference on Electronics Packaging 2016, 451-455, Sapporo, Apr. 2016.
・　Ali Ashikin Binti Fara, Akihiro Odoriba, Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests of Capacitive Open Defects at BGA ICs in Assembled PCB, Proc. of International Forum on Advanced Technologies 2016, 229-231, Tokushima, Mar. 2016.
・　Shyue-Kung Lu, Shu-Chi Yu and Masaki Hashizume : Hybrid Scrambling Technique for Increasing the Fabrication Yield of NROM-Based ROMs, Proc. of International Forum on Advanced Technologies 2016, 207-209, Tokushima, Mar. 2016.
・　Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Die Design for Cost reduction of 3F Stacked Memory ICs, Proc. of International Forum on Advanced Technologies 2016, 79-80, Tokushima, Mar. 2016.
・　Masaki Hashizume, Yuki Ikiri, Shoichi Umezu, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Feasibility of Electrical Test for Open Defects at Address Bus in 3D Memory IC, Proc. of International Forum on Advanced Technologies 2016, 51-53, Tokushima, Mar. 2016.
・　Shyue-Kung Lu, Shu-Chi Yu and Masaki Hashizume : Synergistic Built-in Self-Repair Techniques for Enhancing Fabrication Yield of Embedded Memories, Proc. of International Forum on Advanced Technologies 2016, 59-61, Tokushima, Mar. 2016.

<2015年>
・　Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume and Jiann-Liang Chen : Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs, IEEE Transactions on Computers, Vol.64, No.5, 1230-1240, 2015.
・　Shyue-Kung Lu, Tsai Cheng-Ju and Masaki Hashizume : Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories, Proc. of 2015 IEEE 24th Asian Test Symposium, 49-54, Nov. 2015.
・　Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Test Circuit for Electrical Interconnect Tests of 3D ICs without Boundary Scan Flip Flops, Proc. of the 16th IEEE Workshop on RTL and High Level Testing, 23-28, Mumbai, Nov. 2015.
・　Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test Method of 3D ICs without Boundary Scan Flip Flops, Proc. of IEEE CPMT Symposium Japan 2015, 136-139, Kyoto, Nov. 2015.
・　Shyue-Kung Lu, Hao-Wei Lin and Masaki Hashizume : An Enhanced Built-In Self-Repair Technique For Yield And Reliability Improvement Of Embedded Memories, Proc. of 2015 IEEE 11th International Conference on ASIC (ASICON), 1-4, Chengdu, China, Nov. 2015.
・　Akihiro Odoriba, Masaki Hashizume, Shoichi Umezu and Hiroyuki Yotsuyanagi : A Design for Testability with nMOS Switches to Detect Open pins in Assembled PCBs, Proc. of International Design and Concurrent Engineering Conference 2015, 31-1-31-6, Tokushima, Sep. 2015.
・　Hiroyuki Yotsuyanagi, Akihiro Fujiwara and Masaki Hashizume : On TSV Array Defect Detection Method Using Two Ring-oscillators Considering Signal Transitions at Adjacent TSVs, Proc. of IEEE 3D System Integration Conference 2015, TS8.24.1-TS8.24.4, Sep. 2015.
・　Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test Method of 3D ICs by Injected Charge Volume, Proc. of IEEE 3D System Integration Conference 2015, TS8.19.1-TS8.19.5, Sendai, Sep. 2015.
・　Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test of 3D ICs Made of Dies without ESD Protection Circuits with a Built-in Test Circuit, Proc. of IEEE 3D System Integration Conference 2015, TS8.22.1-TS8.22.5, Sendai, Sep. 2015.
・　Masaki Hashizume, Singo Saijyo and Hiroyuki Yotsuyanagi : Electrically Testable CMOS Image Pixel Circuit, Proc. of IEEE 2015 European Conference on Circuit Theory and Design, 1-4, Trondheim, Aug. 2015.
・　Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Electrical Test for Open Defects in CMOS ICs by Injected Charge, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015, 653-656, Seoul, Jun. 2015.
・　Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Repair Circuit of TSVs in a 3D Stacked Memory IC, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015, 431-434, Seoul, Jun. 2015.
・　Shyue-Kung Lu, Shu-Ling Lin, Hao-Wei Lin and Masaki Hashizume : Hybrid Scrambling Technique for Increasing the Fabrication Yield of NROM-Based ROMs, Proc. of 2015 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, Hsinchu, Taiwan, Apr. 2015.
・　Akihiro Odoriba, Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Ali Ashikin Binti Fara and Shyue-Kung Lu : A Testable Design for Electrical Interconnect Tests of 3D ICs, Proceedings of 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference, 718-722, Kyoto, Japan, Apr. 2015.
・　Shyue-Kung Lu, Cheng-Ju Tsai and Masaki Hashizume : Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories, Proc. of International Forum on Advanced Technologies 2015, 68-69, Tokushima, Mar. 2015.
・　Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin and Masaki Hashizume : Built-in Scrambling Analysis for Yield Enhancement of Embedded Memories, Proc. of International Forum on Advanced Technologies 2015, 44-45, Tokushima, Mar. 2015.
・　Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Switch Circuit for Repairing Defective TSVs in a 3D Stacked Memory IC, Proc. of International Forum on Advanced Technologies 2015, 160-161, Tokushima, Mar. 2015.
・　Masaki Hashizume : Electrical Interconnect Test Method of 3D ICs, 2015 UT and Taiwan Tech Joint Workshop on Advanced VLSI Design Technologies, Taipei, Mar. 2015.

<2014年>
・　Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Supply Current Test Circuit for Electrical Interconnect Tests of 3D ICs, Proc. of IEEE 3D System Integration Conference 2014, O7-1-O7-6, Kinsdale, Ireland, Dec. 2014.
・　Chih-Chan Fang, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Test Pattern Matching Method on BAST Architecture for Test Data Reduction by Controlling Scan Shift, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 130-134, Nov. 2014.
・　Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On SAT-based Test Generation for Resistive Open Using Delay Variation Caused by Effect of Adjacent Lines, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 49-53, Nov. 2014.
・　Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Threshold Setting of Electrical Test Method for Open Defects at Data Bus in 3D SRAM IC, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 64-68, Nov. 2014.
・　Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume and Seiji Kajihara : Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories, Proc. of 2014 IEEE 23rd Asian Test Symposium, 137-142, Nov. 2014.
・　Kousuke Nambara, Shoichi Umezu, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Threshold Value Estimation of Electrical Interconnect, Proc. of IEEE CPMT Symposium Japan 2014, 158-161, Nov. 2014.
・　Hiroyuki Yotsuyanagi, Hiroki Sakurai and Masaki Hashizume : Delay Line Embedded in Boundary Scan for Testing TSVs, Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Seattle, Oct. 2014.
・　Masaki Hashizume, Shohei Suenaga and Hiroyuki Yotsuyanagi : A Built-in Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs, Proc. of the 3rd International Conference on Design and Concurrent Engineering, Sep. 2014.
・　Shyue-Kung Lu, Huai-Min Li, Masaki Hashizume, Jin-Hua Hong and Zheng-Ru Tsai : Efficient Test Length Reduction Techniques for Interposer-based 2.5D ICs, Proc. of 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, Hsinchu, Taiwan, Apr. 2014.
・　Yudai Shiraishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu : Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC, Proc. of International Conference on Electronics Packaging 2014, 235-238, Apr. 2014.
・　Shoichi Umezu, Masaki Hashizume and Hiroyuki Yotsuyanagi : A Built-in Supply Current Test Circuit for Pin Opens in Assembled PCBs, Proceedings of International Conference on Electronics Packaging 2014, 227-230, Toyama, Apr. 2014.
・　Akira Ono, Hiroyuki Yotsuyanagi and Masaki Hashizume : Pin Open Detection of BGA IC by Supply Current Testing, Proceedings of International Conference on Electronics Packaging 2014, 231-234, Toyama, Japan, Apr. 2014.

<2013年>
・　Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.12, 2561-2567, 2013.
・　橋爪 正樹, 小西 朝陽, 四柳 浩之 : 3次元実装IC内ダイ間論理信号線の断線に対する電気テスト用回路, 電子情報通信学会論文誌(C), Vol.J96-C, No.11, 361-370, 2013年.
・　Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya and Masaki Hashizume : On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan, IEICE Transactions on Information and Systems, Vol.E96-D, No.9, 1986-1993, 2013.
・　Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : DFT for Supply Current Testing to Detect Open Defects at Interconnects in 3D ICs, Proc. of IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, 60-63, Nara, Dec. 2013.
・　Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On SAT-based Test Generation for Observing Delay Variation Caused by a Resistive Open Fault and Its Adjacent Lines, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, IV.2.F-1-IV.2.F-6, Yilan,Taiwan, Nov. 2013.
・　Akira Ono, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Supply Current Test Method for Pin Open Defects in Assembled PCB Circuits, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, I.3.S-1-I.3.S-4, Yilan,Taiwan, Nov. 2013.
・　Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : Feasibility of Interconnect Tests of Open Defects in a 3D IC with a Built-in Supply Current Test Circuit, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, I.1.F-1-I.1.F-5, Yilan,Taiwan, Nov. 2013.
・　Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Masaki Hashizume and K. Kewal Saluja : Diagnosing Resistive Open Faults Using Small Delay Fault Simulation, Proc.of IEEE 22th Asian Test Symposium, 79-84, Yilan,Taiwan, Nov. 2013.
・　Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang and Pony Ning : Fault Scrambling Techniques for Yield Enhancement of Embedded Memories, Proc.of IEEE 22th Asian Test Symposium, 215-220, Yilan,Taiwan, Nov. 2013.
・　Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs, Proc.of IEEE 22th Asian Test Symposium, 13-18, Yilan,Taiwan, Nov. 2013.
・　Ei Haraguchi, Masaki Hashizume, Katsuya Manabe, Hiroyuki Yotsuyanagi, Tetsuo Tada, Shyue-Kung Lu and Zvi Roth : Reduction Method of Number of Electromagnetic Simulation Times for Estimating Output Voltage at Hard Open TSV in 3D IC, Proc. of IEEE CPMT Symposium Japan(ICSJ2013), 251-254, Kyoto, Nov. 2013.
・　Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu : Built-in IDDT Appearance Time Sensor for Detecting Open Faults in 3D IC, Proc. of IEEE CPMT Symposium Japan(ICSJ2013), 247-250, Kyoto, Nov. 2013.
・　Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masanori Nakamura and Masaki Hashizume : Time-to-Digital Converter Embedded in Boundary-Scan Circuit and Its Application to 3D iC Testing, International Test Conference 2013, PO30, Anaheim, Sep. 2013.
・　Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testability of Open Defects at Interconnections in 3D ICs with a Built-in Test Circuit for Supply Current Testing, International Test Conference 2013, PO29, Anaheim, Sep. 2013.
・　Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Defect Detection in Assembled PCBs by Supply Current Testing with Electrodes Embedded inside ICs, Proceedings of ICEP2013, 451-456, Osaka, Japan, Apr. 2013.
・　Masaki Hashizume, Masatake Akutagawa, Shyue-Kung Lu and Hiroyuki Yotsuyanagi : Electrical Test Method of Open Defects at Bi-directional Interconnects in 3D ICs, Proceedings of ICEP2013, 13-18, Osaka, Japan, Apr. 2013.
・　Widianto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Size Reduction of a Built-in Test Circuit for Locating Open Interconnects in 3D ICs, Proc. of International Conference on Electronics, Information and Communication, 302-303, Bali, Indonesia, Feb. 2013.

<2012年>
・　Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Electrical Test Method for Interconnect Open Defects in 3D ICs, Transactions of The Japan Institute of Electronics Packaging, Vol.5, No.1, 26-33, 2012.
・　Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Zvi Roth and Masaki Hashizume : A Built-in Electrical Test Circuit for Interconnect tests in Assembled PCBs, Proc. of IEEE CPMT Symposium Japan 2012, 201-204, Kyoto, Dec. 2012.
・　Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : On Detectability Analysis of Open Faults Using SAT-based Test Pattern Generation Considering Adjacent Lines, Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, 2.1.1-2.1.6, Niigata, Nov. 2012.
・　Masaki Hashizume, Shohei Kondo, Ei Haraguchi, Hiroyuki Yotsuyanagi, Tetsuo Tada and Zvi Roth : Output Voltage Estimation Method of Hard Open TSV in 3D ICs, Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, 6.1.1-6.1.5, Niigata, Nov. 2012.
・　Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi : Electrical Interconnect Testing of Open Defects in Assembled PCBs Utilizing IEEE 1149.1 Test Mechanism, International Test Conference 2012, PO1, Anaheim, Nov. 2012.
・　Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Test Circuit for Supply Current Testing of Open Defects at Interconnects in 3D ICs, Proc. of 4-th Electronics System Integration Technologies Conference(ESTC 2012), PA21.1_1-PA21.1_6, Amsterdam, Sep. 2012.
・　Takahashi Hiroshi, Higami Yoshinobu, Yamazaki Koji, Tsutsumi Toshiyuki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation for Resistive Open Faults with Considering Adjacent Lines, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, P-T2-06-1-P-T2-06-4, Sapporo, Jul. 2012.
・　Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Sensor for IDDT Testing of CMOS ICs, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, E-M2-05-1-E-M2-05-4, Sapporo, Jul. 2012.
・　Shingo Saijo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : Testable Design of CMOS Image Pixel Circuits for Electrical Testing, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, D-W2-04-1-D-W2-04-4, Sapporo, Jul. 2012.
・　Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : An Electrical Test Circuit for Detecting Interconnect Open Defects in 3D ICs, Proceedings of ICEP2012, 88-93, Tokyo, Japan, Apr. 2012.
・　Ei Haraguchi, Shohei Kondo, Katsuya Manabe, Hiroyuki Yotsuyanagi and Masaki Hashizume : Output Voltage of a Floating Metal Line Caused by a Neighboring Metal Line Bending at a Right Angle, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 233-236, Honolulu, Mar. 2012.
・　Yasuhiko Okada, Hiroyuki Yotsuyanagi and Masaki Hashizume : The Test Vector Compaction Considering Compatible Flip-Flops for BIST-Aided Scan Test, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 449-452, Honolulu, Mar. 2012.
・　Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Measuring Timing Slack Using Boundary Scan with Time-to-Digital Converter for Detecting Delay Faults, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 445-448, Honolulu, Mar. 2012.
・　Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Supply Current Testing of Open Defects at Interconnects in 3D ICs with IEEE 1149.1 Architecture, International 3D System Integration Conference, 8-2-1-8-2-6, Osaka, Feb. 2012.
・　Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi and Masaki Hashizume : A Built-in Test Circuit for Open Defects at Interconnects between Dies in 3D ICs, International 3D System Integration Conference, P-2-31-1-P-2-31-5, Osaka, Feb. 2012.

<2011年>
・　橋爪 正樹, 加藤 健二, 四柳 浩之 : IEEE1149.1準拠IC間断線の電気検査法, エレクトロニクス実装学会誌, Vol.14, No.2, 99-102, 2011年.
・　Hiroyuki Yotsuyanagi, Hiroyuki Makimoto and Masaki Hashizume : A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing, Proc. 20th Asian Test Symposium, 539-544, New Delhi, Nov. 2011.
・　Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : A Supply Current Testable Register String DAC of Decoder Type, Proc. of 11th International Symposium on Communications and Information Technologies, 58-63, China, Hangzhou, Oct. 2011.
・　Lee Heejin, Hiroyuki Yotsuyanagi, Sohn Kyungrak and Masaki Hashizume : Feasibility of Operating Point Estimation in Lighting Circuit with Measured I-V Characteristics of LEDs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 1026-1029, Gyeongju, Korea, Jun. 2011.
・　Yoshihiko Miyamori, Hiroyuki Yotsuyanagi and Masaki Hashizume : Practical Testability of Supply Current Testable DACs of Resistor Type, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 1015-1018, Gyeongju, Korea, Jun. 2011.
・　Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of Electrical Testing for Lead Opens of QFP ICs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 688-691, Gyeongju, Korea, Jun. 2011.
・　Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Faulty Effect of Soft Open Defect in TSV Caused by Logic Values of Neighboring TSVs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 692-695, Gyeongju, Korea, Jun. 2011.
・　Katsuya Manabe, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu and Masaki Hashizume : Estimation of Faulty Effects Caused by a Clack at an Interconnect Line in 90nm ICs, Proceedings of ICEP2011, 737-742, Nara, Japan, Apr. 2011.
・　Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Fault Analysis of Soft Open Defects in TSVs with Electromagnetic Simulator, Proceedings of ICEP2011, 727-731, Nara, Japan, Apr. 2011.
・　Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : A Supply Current Testable DAC of Resistor String Type, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 13-16, TianJin,China, Mar. 2011.

<2010年>
・　山崎 浩二, 堤 利幸, 高橋 寛, 樋上 喜信, 相京 隆, 四柳 浩之, 橋爪 正樹, 高松 雄三 : 故障励起関数を利用したオープン故障の診断法, 電子情報通信学会論文誌(D), Vol.J93-D, No.11, 2416-2425, 2010年.
・　Masashi Ishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Data Reduction for BIST-aided Scan Test Using Compatible Flip-flops and Shifting Inverter Code, Proc. of 19th Asian Test Symposium, 163-166, Shanghai, Dec. 2010.
・　Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Method for Diagnosing Resistive Open Faults with Considering Adjacent Lines, Proc. of 10th International Symposium on Communications and Information Technologies, 609-614, Tokyo, Oct. 2010.
・　Katsuya Manabe, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu and Masaki Hashizume : Output Voltage Estimation of a Floating Interconnect Line Caused by a Hard Open in 90nm ICs, Proc. of 10th International Symposium on Communications and Information Technologies, 603-608, Tokyo, Oct. 2010.
・　Lee Heejin, Hiroyuki Yotsuyanagi and Masaki Hashizume : Lighting Circuit Analysis Method with Measured I-V Characteristics of LEDs, Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, pp.1262--1265, Pattaya,Thailand, Jul. 2010.
・　Masaki Hashizume, Kondo Shohei and Hiroyuki Yotsuyanagi : Possibility of Logical Error Caused by Open Defects in TSVs, Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, pp.907--910, Pattaya,Thailand, Jul. 2010.
・　Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukunori Nakajima and Kozo Kinoshita : Current-Based Testable Design of Level Shifters in Liquid Crystal Display Drivers, Proc. of 2010 15th European Test Symposium, p.262, Prague, May 2010.
・　Masaki Hashizume, Kenichi Uchikura, Akira Ono, Hiroyuki Yotsuyanagi and Masao Takagi : Built-in Test Circuit for Opens at Interconnects between Dies inside SiPs, Proceedings of ICEP2010, pp.705--710, Sapporo, Japan, Apr. 2010.
・　Shohei Kondo, Katsuya Manabe, Masao Takagi, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Faulty Effects on Logic Signal of a Hard Open Via from Adjacent Ones, Proceedings of ICEP2010, pp.711--715, Sapporo, Japan, Apr. 2010.
・　Hiroyuki Yotsuyanagi, Masaki Hashizume and Masayuki Yamamoto : Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops, IEICE Transactions on Information and Systems, Vol.E93-D, No.1, pp.10-16, 2010.

<2009年>
・　Ryota Kuribayashi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation for Open Faults Considering the Effects of Adjacent Lines, 10th IEEE Workshop on RTL and High Level Testing (WRTLT09), pp.61--66, Hong Kong, Nov. 2009.
・　Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : New Class of Tests for Open Faults with Considering Adjacent Lines, Proc. of 18th Asian Test Symposium, pp.305--310, Taichung, Taiwan, Nov. 2009.
・　Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, pp.794--796, Jeju,Korea, Jul. 2009.
・　Toshiyuki Tsutsumi, Yasuyuki Kariya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Preliminary Analysis of Interconnect Full Open Faults using TEG chips, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, pp.679--682, Jeju, Korea, Jul. 2009.
・　Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : Current Testble Design of Resistor String DACs for Short Defects, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, pp.428--431, Jeju,Korea, Jul. 2009.
・　Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Lead Detection of QFP ICs Using Logic Gates as Open Sensors, Proc. of 2009 International Conference on Electronics Packaging, pp.434--439, Kyoto,Japan, Apr. 2009.
・　Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC, Proc. of 22nd International Conference on VLSI Design, pp.91--96, New Delhi, India, Jan. 2009.
・　Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Novel Approach for Improving the Quality of Open Fault Diagnosis, Proc. of 22nd International Conference on VLSI Design, pp.85--90, New Delhi, India, Jan. 2009.
・　小野 安季良, 一宮 正博, 四柳 浩之, 高木 正夫, 橋爪 正樹 : CMOSゲート回路を断線センサとして用いた部品結合不良検出法, エレクトロニクス実装学会誌, Vol.12, No.2, pp.137-143, 2009.

<2008年>
・　Masayuki Yamamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Scan Chain Configuration for BIST-aided Scan Test using Compatible Scan Flip-flops, 9th Workshop on RTL and High Level Testing (WRTLT08), pp.99--104, Sapporo, Nov. 2008.
・　Masaki Hashizume, Akihito Shimoura, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Test Circuit for Locating Open Leads of QFP ICs, IEEE 7-th International Board Test Workshop, Fort Collins, USA, Sep. 2008.
・　Yutaka Hata, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura : Current Testble Design of Resistor String DACs for Open Defects, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, pp.1533--1536, Shimonoseki, Japan, Jul. 2008.
・　Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, pp.241--244, Shimonoseki,Japan, Jul. 2008.
・　Masaki Hashizume, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Fault Analysis of Interconnect Opens in 90nm ICs with Device Simulator, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, pp.249--252, Shimonoseki, Japan, Jul. 2008.
・　Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Test Method for DetectingOpen Leads of Low Voltage LSIs, Proceedings of ICEP2008, pp.457--462, Tokyo, Jun. 2008.

<2007年>
・　高木 正夫, 橋爪 正樹, 一宮 正博, 四柳 浩之 : 交流電界印加時の電流テストによるCMOS LSIのリード浮き検出のための印加交流電圧, エレクトロニクス実装学会誌, Vol.8, No.3, pp.219-228, 2007.
・　Masaki Hashizume, Masahiro Ichimiya, Akira Ono and Hiroyuki Yotsuyanagi : Test Circuit for Vectorless Open Lead Detection of CMOS ICs, IEEE 6-th International Board Test Workshop, Fort Collins, Oct. 2007.
・　Masaki Hashizume, Yuuki Ogata, Mitsuru Tojo, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Interconnect Open Detection by Supply Current Testing under AC Electric Field Application, IEEE International Workshop on Current and Defect Based Testing, pp.25--29, Santa Clara, Oct. 2007.
・　Hiroyuki Yotsuyanagi, Takeshi Iihara and Masaki Hashizume : On SoC Testing Using Multiple Scan Chains with Scan Tree Configurations, 8th Workshop on RTL and High Level Testing (WRTLT07), pp.151--156, Beijing, Oct. 2007.
・　Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi and Yukiya Miura : Current Testable Design of Resistor String DACs, Proc. of 16th Asian Test Symposium, pp.399--403, Beijing, Oct. 2007.
・　Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines, Proc. of 16th Asian Test Symposium, pp.39--44, Beijing, Oct. 2007.
・　Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines, IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp.243--251, Rome, Italy, Sep. 2007.
・　Ono Akira, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Open Lead Detection of CMOS Logic Circuits by Low Pressure Probing, Proceedings of ICEP2007, pp.359--364, Tokyo, Apr. 2007.

<2006年>
・　 Eiji Tasaka, Masaki Hashizume, Seiichi Nishimoto, Hiroyuki Yotsuyanagi, Takahiro Oie, Ikuro Morita and Toshihiro Kayahara : At Speed Testing of Bus Interconnects in Microcomputers, 7th Workshop on RTL and High Level Testing (WRTLT06), pp.123--127, Fukuoka, Nov. 2006.
・　Hiroyuki Yotsuyanagi, Tomohiko Nagashima and Masaki Hashizume : Test Time Reduction for Scan Circuits by Selection of a Flip-flop with Hold Operation, 7th Workshop on RTL and High Level Testing (WRTLT06), pp.81--85, Fukuoka, Nov. 2006.
・　Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura : A BIC Sensor Capable of Adjusting IDDQ Limit in Tests, Proc. of 15th Asian Test Symposium, pp.69--74, Fukuoka, Nov. 2006.
・　Tojo Mitsuru, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Current Testing of Interconnect Opens between CMOS LSIs Having Scan Cells, IEEE International Workshop on Current and Defect Based Testing, pp.39--42, Santa Clara, Oct. 2006.
・　Masaki Hashizume and Hiroyuki Yotsuyanagi : Test Circuit for Open Lead Detection of CMOS ICs Based on Supply Current, the IEEE European Board Test Workshop, Southampton, UK, May 2006.
・　Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application, Proceedings of ICEP2006, pp.147--152, Tokyo, Apr. 2006.
・　Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Time Reduction Method for Scan Design with Clock-Control DFT, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.441--444, Honolulu, Mar. 2006.
・　Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura : Current Testable Design of Registor String DACs, the IEEE International Workshop on Electronic Design, Test and Applications, pp.197--200, Kuala Lumpur, Malaysia, Jan. 2006.

<2005年>
・　Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita : Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees, Journal of Electronic Testing: Theory and Applications, Vol.21, No.6, pp.613-620, 2005.
・　月本 功, 橋爪 正樹, 四柳 浩之, 為貞 建臣 : ばらつきを有するICで構成したTTL回路の電源電流による統計的断線故障検出法, エレクトロニクス実装学会誌, Vol.8, No.3, pp.199-207, 2005.
・　Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops, 6th Workshop on RTL and High Level Testing (WRTLT05), pp.79--83, Harbin, China, Jul. 2005.
・　Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing, Proc. of IEEE International Symposium on Circuits and Systems, pp.2995--2998, Kobe, May 2005.
・　Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Vectorless Open Pin Detection Method for CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, pp.391--396, Tokyo, Apr. 2005.
・　Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara : Fail-Safe Evaluation Method for Boiler Control Circuits by Circuit Simulation, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.395--398, Honolulu, Mar. 2005.
・　Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electrical Detection of Pin Shorts by Supply Current of PIC, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.171--174, Honolulu, Mar. 2005.
・　Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application, Proc. of the ECWC 10 Conference, pp.P03-5-1--P03-5-5, Anaheim, Feb. 2005.

<2004年>
・　Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto : Genetic State Reduction Method of Incompletely Specified Machines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, pp.1555-1563, 2004.
・　Masao Takagi, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Lead Open Detection Based on Supply Current of CMOS LSIs, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, pp.1330-1337, 2004.
・　Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Sequence Generation for Test Time Reduction of IDDQ Testing, IEICE Transactions on Information and Systems, Vol.E87-D, No.3, pp.537-543, 2004.
・　Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits, IEICE Transactions on Information and Systems, Vol.E87-D, No.3, pp.571-579, 2004.
Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita and Takeomi Tamesada : IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment, Proc. of 13th Asian Test Symposium, pp.112--117, Kenting, Taiwan, Nov. 2004.
・　Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application, Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems, pp.I-557--I-560, Hiroshima, Jul. 2004.
・　Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Tsukimoto Isao and Takeomi Tamesada : AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs, Proc. of International Conference on Electronics Packaging, pp.217--222, Tokyo, Apr. 2004.
・　Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, pp.306--311, Perth, Australia, Jan. 2004.
・　Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita : On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, pp.269--274, Perth, Australia, Jan. 2004.
・　Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Practical Fault Coverage of Supply Current Tests for Bipolar ICs, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, pp.189--194, Perth, Australia, Jan. 2004.
・　Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Fault Detection by Appearance Time of Switching Supply Current, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, pp.183--188, Perth, Australia, Jan. 2004.

<2003年>
・　Hiroyuki Yotsuyanagi, Taisuke Iwakiri, Masaki Hashizume and Takeomi Tamesada : Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field, IEICE Transactions on Information and Systems, Vol.E86-D, No.12, pp.2666-2673, 2003.
・　橋爪正樹，田坂英司，四柳浩之，為貞建臣，茅原敏広，森田郁朗，大家隆弘 : CMOSマイクロコンピュータ回路の電源電流によるブリッジ故障検出法，エレクトロニクス実装学会誌，Vol.6, No.7, pp.564-572, Nov., 2003
・　H.Yotsuyanagi, T.Kuchii, S.Nishikawa, M.Hashizume, K.Kinoshita : Reducing Scan Shifts using Folding Scan Trees, Proc. of the 12-th IEEE Asian Test Symposium, Nov., 2003
・　M.Hashizume, T.Takeda, H.Yotsuyanagi, T.Tamesada, Y.Miura, K.Kinoshita : A BIST Circuit for IDDQ Tests, Proc. of the 12-th IEEE Asian Test Symposium, Nov., 2003
・　M.Takagi, M.Hashizume, M.Ichimiya, H.Yotsuyanagi, T.Tamesada : Testability of Pin Open in Small Outline Package ICs by Supply Current Test, Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications, pp.836-839, July, 2003
・　M.Hashizume, M.Kawajiri, H.Yotsuyanagi, T.Tamesada : Testability of Supply Current Test in an AGC Circuit, Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications, pp.836-839, July, 2003,
・　一宮正博，橋爪正樹，四柳浩之，為貞建臣 : CMOS論理ICの交流電界印加時の電源電流測定によるピン浮き検出法, エレクトロニクス実装学会誌, Vol.6, No.2, pp140-146, June, 2003
・　一宮正博，橋爪正樹，四柳浩之，為貞建臣 : CMOS論理回路の発振を生じるICピン短絡故障検出回路，電子情報通信学会論文誌D-I，Vol.J86-D-I, No.6, pp.402-411，June, 2003
・　M.Hashizume, M.Ichimiya, H.Yotsuyanagi and T.Tamesada : Electric Field Application Method Effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits, Proc. of the 2003 International Conference on Electronics Packaging, pp.75-80, April, 2003

<2002年>
・　H.Yotsuyanagi, M.Hashizume, T.Tamesada : Test Time Reduction for IDDQ Testing by Arranging Test Vectors, Proc. of the 11-th IEEE Asian Test Symposium, pp.423-428, Nov., 2002
・　Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States, IEICE Transactions on Information and Systems, Vol.E85-D, No.10, pp.1605-1608, 2002.
・　M.Hashizume, Y.Matsushima, T.Shimamoto, H.Yotsuyanagi, T.Tamesada and A.Sakamoto : Simplification of Incompletely Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism, Proc. of the IEEE 3rd Workshop on RTL and High Level Testing(WRTLT2002), pp.74-78, Nov., 2002
・　M.Hashizume, M.Ichimiya, H.Yotsuyanagi , T.Tamesada : Pin Open Detection of CMOS Logic ICs by Supply Current Measurement under Time-Varying Magnetic Field Application, Proc. of 9-th Electronic Circuits World Convention, PD-1-PD-4, Oct., 2002
・　M.Hashizume, T.Takeda, M.Ichimiya, H.Yotsuyanagi, Y.Miura, K.Kinoshita : IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates, IEICE Trans. on Inf.&Syst. Vol. E85-D, No.10, pp.1534-1541, Oct., 2002
・　M.Hashizume, M.Ichimiya, H.Yotsuyanagi, T.Tamesada : CMOS Open Defect Detection by Supply Current Measurement under Time-variable Electric Field Supply, IEICE Trans. on Inf.&Syst. Vol.E85-D, No.10, pp.1542-1550, Oct., 2002
・　H.Yotsuyanagi, M.Hashizume, T.Tamesada : Sequential Redunduncy Removal Using Test Generation and Multiple Strongly Unreachable States, IEICE Trans. on Inf.&Syst. Vol.E85-D, No.10, pp.1605-1608, Oct., 2002
・　M.Hashizume，N.Inou，H.Yotsuyanagi，T.Tamesada : Oscillation Frequency Estimation for Detecting Feedback Bridging Faults, Proc. of 2002 International Technical Conference on Circuits/Systems, Computers and Communications，Vol.3，pp.1980-1983，July 2002.
・　I.Tsukimoto，M.Hashizume，Y.Mushiaki，H.Yotsuyanagi，T.Tamesada : Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits, Proc. of 2002 International Technical Conference on Circuits/Systems, Computers and Communications，Vol.3，pp.1972-1975，July 2002.
・　M.Hashizume，E.Tasaka, M.Ichimiya, H.Yotsuyanagi，T.Tamesada, T.Kayahara : Power-off Vectorless Test Method for Pin Opens in CMOS Logic Circuits, Proc. of Electronics Packaging, pp.363-368，April 2002.
・　M.Hashizume，M.Ichimiya，H.Yotsuyanagi，T.Tamesada : Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits, Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications，pp.459-461，Jan. 2002.
・　M.Hashizume，M.Sato，H.Yotsuyanagi，T.Tamesada : Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits, Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications，pp.459-461，Jan. 2002.
・　H.Yotsuyanagi，M.Hashizume，T.Iwakiri，M.Ichimiya，T.Tamesada : Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field, Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications，pp.387-391，Jan. 2002.

<2001年>
・　M.Hashizume，M.Ichimiya，H.Yotsuyanagi，T.Tamesada : CMOS Open Defect Detection Based on Supply Current in Time-variable Electric Field and Supply Voltage Application, Proc. of Tenth Asian Test Symposium，pp.117-122，Nov. 2001.
・　T.Takeda，M.Hashizume，M.Ichimiya，H.Yotsuyanagi，Y.Miura，K.Kinoshita : IDDQ Sensing Technique for High Speed IDDQ Testing, Proc. of Tenth Asian Test Symposium，pp.111-116，Nov. 2001
・　H.Yotsuyanagi，S.Hata，M.Hashizume，T.Tamesada : Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States, Proc. of Tenth Asian Test Symposium，pp.23-28，Nov. 2001.
・　H.Yotsuyanagi，M.Hashizume，T.Iwakiri，M.Ichimiya，T.Tamesada : Test Pattern for Supply Current Test of Open Defects by Applying Time-variable Electric Field, Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems，pp.287-295，Oct. 2001.
・　T.Takeda，M.Hashizume，M.Ichimiya，H.Yotsuyanagi，T.Tamesada : A High Speed IDDQ Sensor Circuit, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications，Vol.2，pp.438-441，July 2001.
・　T.Koyama，M.Hashizume，T.Arakawa，M.Ono : Efficient Test Methods for CMOS SRAMs with Quiescent Write Supply Current, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications，Vol.1，pp.434-437，July 2001.
・　M.Hashizume，E.Tasaka，H.Yotsuyanagi，T.Tamesada，T.Kayahara : Fault Simulator for Test Program Generation in Supply Current Tests of Microprocessor Based Boiler Control Circuits, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications，Vol.1，pp.446-449，July 2001.
・　A.Tsuji，M.Hashizume，M.Ichimiya，H.Yotsuyanagi，T.Tamesada : Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications，Vol.1，pp.438-441，July 2001.
・　M.Hashizume，H.Hoshika，H.Yotsuyanagi，T.Tamesada : Testable Static CMOS PLA for IDDQ Testing, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences，Vol.E84-A，No.6，pp.1488-1495，2001.
・　M.Hashizume，M.Ichimiya, A.Tsuji，H.Yotsuyanagi，T.Tamesada : Supply Current Test for Pin Opens in CMOS Logic Circuits, Proc. of Electronics Packaging, pp.363-368，April 2001.
・　M.Hashizume, M.Ichimiya, H.Yotsuyanagi and T.Tamesada : CMOS Open Defect Detection by Supply Current Test, DATE 2001, pp.509-513, Mar. 2001.

<2000年>
・　M.Hashizume, H.Yotsuyanagi, M.Ichimiya, T.Tamesada and M.Takeda : High Speed IDDQ Test and Its Testability for Process Variation, IEEE Asian Test Symposium, pp.344-349, TAIPEI TAIWAN, Dec. 2000.
・　M.Hashizume, H.Yotsuyanagi, T.Tamesada and M.Takeda : Testable Analysis of IDDQ Testing with Large Threshold Value, IEEE Internatinal Symposium on Defect and Fault Tolerance in VLSI Systems, pp.367-375, Yamanashi Japan, Oct. 2000.
・　H.Yotsuyanagi, M.Hashizume and T.Tamesada : Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.355-358, Pusan, Korea, July 2000.
・　S.Yamamoto, M.Hashizume, H.Yotsuyanagi and T.Tamesada : Oscillation Frequency Estimation of Feedback Bridging Faults for Test Circuit Design, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.343-346, Pusan, Korea, July 2000.
・　H.Hoshika, M.Hashizume, H.Yotsuyanagi and T.Tamesada : IDDQ Testable Design of Static CMOS PLAs with Low Power Consumption, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.351-354, Pusan, Korea, July 2000.
・　T.Ohnishi, H.Yotsuyanagi, M.Hashizume and T.Tamesada : A Test Input Sequence for Test Time Reduction of IDDQ Testing, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.367-370, Pusan, Korea, July 2000.
・　Y.Mushiaki, M.Hashizume, H.Yotsuyanagi and T.Tamesada : Practical Fault Coverage of Supply Current Testing for Open Fault in TTL Combinational Circuits, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.383-386, Pusan, Korea, July 2000.
・　M.Sato, M.Hashizume, H.Yotsuyanagi and T.Tamesada : Power Supply Circuits with Small Size for Adiabatic Dynamic CMOS Logic Circuits, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.179-182, Pusan, Korea, July 2000.
・　H.Yotsuyanagi, M.Hashizume and T.Tamesada : Adding Transitions of Undefined States to State Transition Tables for Testability Enhancement, Workshop on RTL ATPG & DFT (WRTLT00), Sep. 2000.
・　M.Hashizume,H.Hoshika,H.Yotsuyanagi,T.Tamkesada : IDDQ Testable Design of Static CMOS PLAs, Proc. of the IEEE International Workshop on Defect Based Testing, pp.70-75(2000)

<1999年>
・　M.Hashizume,S.Yamamoto,H.Yotsuyanagi,T.Tamesada: Identification of Feedback Bridging Faults with Oscillation, Proc. of the IEEE 8-th Asian Test Symposium,pp.25-30(1999)
・　M.Hashizume，H.Yotsuyanagi，T.Tamesada，E.Tasaka，T.Kayahara: Supply Current Testing for Bridging Faults in Microprocessor Based Sequence Control Circuits, Proc. of the 8-th Electronic CircuitsWorld Convention,pp.T2-3-1-T2-3-7(1999).
・　橋爪正樹，為貞建臣，小山健，AJ van de Goor:"CMOS　SRAM　ICの書き込み時静的電源電流による論理故障検出法",電子情報通信学会論文誌,Vol.J82-D-I,No.7,pp.906-915(1999).
・　M.Hashizume, M.Sato,H.Yotsuyanagi,T.Tamesada : Power Supply Circuit for Adiabatic Dynamic CMOS Logic Circuits, Proc. of 1999 International Techinical Conference on Circuits/Systems, Computers and Communications,pp162-165(1999).
・　M.Hashizume, T.Matsushima,T.Tamesada, T.Shimamoto, A.Sakamoto : State Reduction of Incompletely Specified Machines Based on Genetic Approach, Proc. of 1999 International Techinical Conference on Circuits/Systems, Computers and Communications,pp.888-891(1999)

<1998年>
・　M.Hashizume, Y.Miura,M.Ichimiya,T.Tamesada, K.Kinoshita : A High Speed IDDQ Sensor for Low Voltage ICs, Proc. of the IEEE Seventh Asian Test Symposium,pp.327-331,(1998)
・　M.Hashizume，T.Tamesada，T.Shimamoto，A.Sakamot : Heuristic State Reduction Methods of Incompletely Specified Machines Proceding to Satisfy Covering Condition, IEICE Trans.Fundamentals,Vol.E81-A,No.6,pp.1045-1054(1998).
・　T.Kuchi,M.Hashizume, T.Tamesada : Test Input Generation for Supply Current Testing of Bridging Faults in Bipolar Combinational Logic Circuits, Proc. of IEEE International Workshop on IDDQ Testing,pp.14-18(1998)
・　M.Hashizume,T.Tamesada,T.Koyama,,A.J.van de Goor : CMOS SRAM Functional Test with Quiescent Write Supply Current, Proc. of IEEE International Workshop on IDDQ Testing,pp.4-8(1998).
・　口井敏匡，橋爪正樹，為貞建臣:"プリント回路板上のTTL組み合わせ回路の電源電流による断線故障検出法",エレクトロニクス実装学会誌,Vol.1,No.4，pp.284-293(1998)

<1997年>
・　M.Hashizume, T.Kuchii, T.Tamesada : Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates, Proc. of the IEEE Sixth Asian Test Symposium,pp.372-377(1997)
・　M.Hashizume, M.Ichimiya, T.Tamesada : A Current Sensing Circuit for Feedback Bridging Faults, Proc. of the IEEE International Workshop on IDDQ Testing,pp.110-113(1997).