Publication List

(Updated on June 28, 2015)
Current Research Topics
Publication List(only from 1997)
  1. Akihiro Odoriba, Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Ali Ashikin Binti Fara and Shyue-Kung Lu :
    A Testable Design for Electrical Interconnect Tests of 3D ICs ,
    Proc. of 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference, pp.718-722, 2015.
  2. Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume, Jiann-Liang Chen :
    Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs ,
    IEEE Transactions on Computers, Vol.64, No.5, pp.1230-1240,2014.
  3. Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
    A Built-in Supply Current Test Circuit for Electrical Interconnect Tests of 3D ICs ,
    Proc. of IEEE 3D System Integration Conference 2014, pp.O7-1-O7-6, 2014.
  4. Chih-Chan Fang, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    A Test Pattern Matching Method on BAST Architecture for Test Data Reduction by Controlling Scan Shift ,
    Proc. of the 15th IEEE Workshop on RTL and High Level Testing, pp.130-134, 2014.
  5. Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
    On SAT-based Test Generation for Resistive Open Using Delay Variation Caused by Effect of Adjacent Lines ,
    Proc. of the 15th IEEE Workshop on RTL and High Level Testing, pp.49-53, 2014.
  6. Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu :
    Threshold Setting of Electrical Test Method for Open Defects at Data Bus in 3D SRAM IC ,
    Proc. of the 15th IEEE Workshop on RTL and High Level Testing, pp.64-68, 2014.
  7. Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume and Seiji Kajihara :
    Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories ,
    Proc. of 2014 IEEE 23rd Asian Test Symposium, pp.137-142, 2014.
  8. Kousuke Nambara, Shoichi Umezu, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
    Threshold Value Estimation of Electrical Interconnect ,
    Proc. of IEEE CPMT Symposium Japan 2014, pp.158-161, 2014.
  9. Hiroyuki Yotsuyanagi, Hiroki Sakurai and Masaki Hashizume :
    Delay Line Embedded in Boundary Scan for Testing TSVs ,
    Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2014.
  10. Masaki Hashizume, Shohei Suenaga and Hiroyuki Yotsuyanagi :
    A Built-in Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs ,
    Proc. of the 3rd International Conference on Design and Concurrent Engineering, 2014.
  11. Yudai Shiraishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu :
    Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC ,
    Proc. of International Conference on Electronics Packaging 2014, pp.235-238, 2014.
  12. Shoichi Umezu, Masaki Hashizume and Hiroyuki Yotsuyanagi :
    A Built-in Supply Current Test Circuit for Pin Opens in Assembled PCBs ,
    Proc. of International Conference on Electronics Packaging 2014, pp.227-230, 2014.
  13. Akira Ono, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Pin Open Detection of BGA IC by Supply Current Testing ,
    Proc. of International Conference on Electronics Packaging 2014, pp.231-234, 2014.
  14. Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
    SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines ,
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.12, pp.2561-2567, 2013.
  15. Masaki Hashizume, Tomoaki Konishi, Hiroyuku Yotsuyanagi:
    Electrical Testable Design for Open Defects at Logic Signal Lines between Dies in 3D ICs ,
    IEICE Trans. on Electronics,Vol.J96-C, No.11, pp.361-370,2013.
  16. Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya and Masaki Hashizume :
    On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan ,
    IEICE Transactions on Information and Systems, Vol.E96-D, No.9, pp.1986-1993, 2013.
  17. LI Tsu-Lin, Masaki Hashizume and Shyue-Kung LU :
    An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs ,
    IEICE Transactions on Information and Systems, Vol.E96-D, No.9, pp.2026-2030, 2013.
  18. Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth :
    DFT for Supply Current Testing to Detect Open Defects at Interconnects in 3D ICs ,
    Proc. of IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, pp.60-63,2013.
  19. Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
    On SAT-based Test Generation for Observing Delay Variation Caused by a Resistive Open Fault and Its Adjacent Lines ,
    Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, pp.IV.2.F-1-IV.2.F-6, 2013.
  20. Akira Ono, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Supply Current Test Method for Pin Open Defects in Assembled PCB Circuits ,
    Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, pp.I.3.S-1-I.3.S-4, 2013.
  21. Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth :
    Feasibility of Interconnect Tests of Open Defects in a 3D IC with a Built-in Supply Current Test Circuit ,
    Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, pp.I.1.F-1-I.1.F-5, 2013.
  22. Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Masaki Hashizume and K. Kewal Saluja :
    Diagnosing Resistive Open Faults Using Small Delay Fault Simulation ,
    Proc. of IEEE 22th Asian Test Symposium, pp.79-84, 2013.
  23. Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang and Pony Ning :
    Fault Scrambling Techniques for Yield Enhancement of Embedded Memories ,
    Proc. of IEEE 22th Asian Test Symposium, pp.215-220, 2013.
  24. Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
    Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs ,
    Proc. of IEEE 22th Asian Test Symposium, pp.13-18, 2013.
  25. Ei Haraguchi, Masaki Hashizume, Katsuya Manabe, Hiroyuki Yotsuyanagi, Tetsuo Tada, Shyue-Kung Lu and Zvi Roth :
    Reduction Method of Number of Electromagnetic Simulation Times for Estimating Output Voltage at Hard Open TSV in 3D IC ,
    Proc. of IEEE CPMT Symposium Japan(ICSJ2013), pp.251-254, 2013.
  26. Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu :
    Built-in IDDT Appearance Time Sensor for Detecting Open Faults in 3D IC ,
    Proc. of IEEE CPMT Symposium Japan(ICSJ2013), pp.247-250, 2013.
  27. Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masanori Nakamura and Masaki Hashizume :
    Time-to-Digital Converter Embedded in Boundary-Scan Circuit and Its Application to 3D iC Testing ,
    International Test Conference 2013, p.PO30, 2013.
  28. Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
    Testability of Open Defects at Interconnections in 3D ICs with a Built-in Test Circuit for Supply Current Testing ,
    International Test Conference 2013, p.PO29, 2013.
  29. Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
    Open Defect Detection in Assembled PCBs by Supply Current Testing with Electrodes Embedded inside ICs ,
    Proc. of ICEP2013, pp.451-456, 2013.
  30. Masaki Hashizume, Masatake Akutagawa, Shyue-Kung Lu and Hiroyuki Yotsuyanagi :
    Electrical Test Method of Open Defects at Bi-directional Interconnects in 3D ICs ,
    Proc. of ICEP2013, pp.13-18, 2013.
  31. Widianto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Size Reduction of a Built-in Test Circuit for Locating Open Interconnects in 3D ICs ,
    Proc. of International Conference on Electronics, Information and Communication, pp.302-303, 2013.
  32. Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Electrical Test Method for Interconnect Open Defects in 3D ICs ,
    Trans. of The Japan Institute of Electronics Packaging, Vol.5, No.1, pp.26-33, 2012.
  33. Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Zvi Roth and Masaki Hashizume :
    A Built-in Electrical Test Circuit for Interconnect tests in Assembled PCBs ,
    Proc. of IEEE CPMT Symposium Japan 2012, pp.201-204, 2012.
  34. Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
    On Detectability Analysis of Open Faults Using SAT-based Test Pattern Generation Considering Adjacent Lines ,
    Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, pp.2.1.1-2.1.6, 2012.
  35. Masaki Hashizume, Shohei Kondo, Ei Haraguchi, Hiroyuki Yotsuyanagi, Tetsuo Tada and Zvi Roth :
    Output Voltage Estimation Method of Hard Open TSV in 3D ICs ,
    Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, pp.6.1.1-6.1.5, 2012.
  36. Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi :
    Electrical Interconnect Testing of Open Defects in Assembled PCBs Utilizing IEEE 1149.1 Test Mechanism ,
    International Test Conference 2012, p.PO1, 2012.
  37. Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    A Built-in Test Circuit for Supply Current Testing of Open Defects at Interconnects in 3D ICs ,
    Proc. of 4-th Electronics System Integration Technologies Conference(ESTC 2012), pp.PA21.1_1-PA21.1_6, 2012.
  38. Takahashi Hiroshi, Higami Yoshinobu, Yamazaki Koji, Tsutsumi Toshiyuki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Test Generation for Resistive Open Faults with Considering Adjacent Lines ,
    Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, pp.P-T2-06-1-P-T2-06-4, 2012.
  39. Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    A Built-in Sensor for IDDT Testing of CMOS ICs ,
    Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, pp.E-M2-05-1-E-M2-05-4, 2012.
  40. Shingo Saijo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
    Testable Design of CMOS Image Pixel Circuits for Electrical Testing ,
    Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, pp.D-W2-04-1-D-W2-04-4, 2012.
  41. Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    An Electrical Test Circuit for Detecting Interconnect Open Defects in 3D ICs ,
    Proc. of ICEP2012, pp.88-93, 2012.
  42. Ei Haraguchi, Shohei Kondo, Katsuya Manabe, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Output Voltage of a Floating Metal Line Caused by a Neighboring Metal Line Bending at a Right Angle ,
    Proc. of RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.233-236, 2012.
  43. Yasuhiko Okada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    The Test Vector Compaction Considering Compatible Flip-Flops for BIST-Aided Scan Test ,
    Proc. of RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.449-452, 2012.
  44. Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    On Measuring Timing Slack Using Boundary Scan with Time-to-Digital Converter for Detecting Delay Faults ,
    Proc. of RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.445-448, 2012.
  45. Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Supply Current Testing of Open Defects at Interconnects in 3D ICs with IEEE 1149.1 Architecture ,
    International 3D System Integration Conference, pp.8-2-1-8-2-6, 2012.
  46. Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi and Masaki Hashizume :
    A Built-in Test Circuit for Open Defects at Interconnects between Dies in 3D ICs ,
    International 3D System Integration Conference, pp.P-2-31-1-P-2-31-5, 2012.
  47. Masaki Hashizume, kenji Kato, Hiroyuki Yotsuyanagi :
    Electrical Testing of Open Defects between IEEE1149.1 Compliand ICs ,
    Journal of Japan Institute of Electronics Packaging, Vol.14, No.2, pp.99-102, 2011.(In Japanese)
  48. Kondo Shohei, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Propagation Delay Analysis of a Soft Open Defect inside a TSV ,
    Transactions of The Japan Institute of Electronics Packaging, Vol.4, No.1, pp.119-126, 2011.
  49. Hiroyuki Yotsuyanagi, Hiroyuki Makimoto and Masaki Hashizume :
    A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing ,
    Proc. of IEEE 20th Asian Test Symposium, pp.539-544, 2011.
  50. Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura :
    A Supply Current Testable Register String DAC of Decoder Type ,
    Proc. of 11th International Symposium on Communications and Information Technologies, pp.58-63, 2011.
  51. Lee Heejin, Hiroyuki Yotsuyanagi, Sohn Kyungrak and Masaki Hashizume :
    Feasibility of Operating Point Estimation in Lighting Circuit with Measured I-V Characteristics of LEDs ,
    Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, pp.1026-1029, 2011.
  52. Miyamori Yoshihiko, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Practical Testability of Supply Current Testable DACs of Resistor Type ,
    Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, pp.1015-1018, 2011.
  53. Konishi Tomoaki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Feasibility of Electrical Testing for Lead Opens of QFP ICs ,
    Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, pp.688-691, 2011.
  54. Kondo Shohei, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Faulty Effect of Soft Open Defect in TSV Caused by Logic Values of Neighboring TSVs ,
    Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, pp.692-695, 2011.
  55. Manabe Katsuya, Hiroyuki Yotsuyanagi, Tsutsumi Toshiyuki, Yamazaki Koji, Higami Yoshinobu, Takahashi Hiroshi, Takamatsu Yuzo and Masaki Hashizume :
    Estimation of Faulty Effects Caused by a Clack at an Interconnect Line in 90nm ICs ,
    Proc. of ICEP2011, pp.737-742, 2011.
  56. Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Fault Analysis of Soft Open Defects in TSVs with Electromagnetic Simulator ,
    Proc. of ICEP2011, pp.727-731, 2011.
  57. Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura :
    A Supply Current Testable DAC of Resistor String Type ,
    Proc. of RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.13-16, 2011.
  58. Koji Yamazaki, Toshiyuki Tsusumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu:
    A Method for Locating Open Faults by Using a Fault Excitation Function ,
    IEICE Transactions on Information and Systems, Vol.J93-D, No.11, pp.2416-2425, 2010(In Japanease)
  59. Hiroyuki Yotsuyanagi, Masaki Hashizume and Masayuki Yamamoto :
    Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops ,
    IEICE Transactions on Information and Systems, Vol.E93-D, No.1, pp.10-16, 2010.
  60. Masashi Ishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Test Data Reduction for BIST-aided Scan Test Using Compatible Flip-flops and Shifting Inverter Code ,
    Proc. of 19th Asian Test Symposium, pp.163-166, 2010.
  61. Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    A Method for Diagnosing Resistive Open Faults with Considering Adjacent Lines ,
    Proc. of 10th International Symposium on Communications and Information Technologies, pp.609-614, 2010.
  62. Katsuya Manabe, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu and Masaki Hashizume :
    Output Voltage Estimation of a Floating Interconnect Line Caused by a Hard Open in 90nm ICs ,
    Proc. of 10th International Symposium on Communications and Information Technologies, pp.603-608, 2010.
  63. Lee Heejin, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Lighting Circuit Analysis Method with Measured I-V Characteristics of LEDs ,
    Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, pp.1262-1265, 2010.
  64. Masaki Hashizume, Kondo Shohei and Hiroyuki Yotsuyanagi :
    Possibility of Logical Error Caused by Open Defects in TSVs ,
    Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, pp.907-910, 2010.
  65. Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukunori Nakajima and Kozo Kinoshita :
    Current-Based Testable Design of Level Shifters in Liquid Crystal Display Drivers ,
    Proc. of 2010 15th European Test Symposium, p.262, 2010.
  66. Masaki Hashizume, Kenichi Uchikura, Akira Ono, Hiroyuki Yotsuyanagi and Masao Takagi :
    Built-in Test Circuit for Opens at Interconnects between Dies inside SiPs ,
    Proc. of ICEP2010, pp.705-710, 2010.
  67. Shohei Kondo, Katsuya Manabe, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Faulty Effects on Logic Signal of a Hard Open Via from Adjacent Ones ,
    Proc. of ICEP2010, pp.711-715, 2010.
  68. Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
    Open Lead Detection Method by Sensing the Switching Current of CMOS Gate on Sensing Probe ,
    Journal of Japan Institute of Electronics Packaging, Vol.12, No.2, pp.137-143, 2009.(in Japanese)
  69. Ryota Kuribayashi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Test Generation for Open Faults Considering the Effects of Adjacent Lines ,
    10th IEEE Workshop on RTL and High Level Testing (WRTLT09), pp.61-66, 2009.
  70. Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    New Class of Tests for Open Faults with Considering Adjacent Lines ,
    Proc. of 18th Asian Test Symposium, pp.305-310, 2009.
  71. Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs ,
    Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, pp.794-796, 2009.
  72. Toshiyuki Tsutsumi, Yasuyuki Kariya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu :
    Preliminary Analysis of Interconnect Full Open Faults using TEG chips ,
    Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, pp.679-682, 2009.
  73. Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura :
    Current Testble Design of Resistor String DACs for Short Defects ,
    Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, pp.428-431, 2009.
  74. Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
    Open Lead Detection of QFP ICs Using Logic Gates as Open Sensors ,
    Proc. of 2009 International Conference on Electronics Packaging, pp.434-439, 2009.
  75. Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu :
    Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC ,
    Proc. of 22nd International Conference on VLSI Design, pp.91-96, 2009.
  76. Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    A Novel Approach for Improving the Quality of Open Fault Diagnosis ,
    Proc. of 22nd International Conference on VLSI Design, pp.85-90, 2009.
  77. Masayuki Yamamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Scan Chain Configuration for BIST-aided Scan Test using Compatible Scan Flip-flops ,
    IEEE 9th Workshop on RTL and High Level Testing (WRTLT08), pp.99-104, 2008.
  78. Masaki Hashizume, Akihito Shimoura, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
    Test Circuit for Locating Open Leads of QFP ICs ,
    IEEE 7-th International Board Test Workshop, 2008.
  79. Yutaka Hata, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura :
    Current Testble Design of Resistor String DACs for Open Defects ,
    Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, pp.1533-1536, 2008.
  80. Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
    Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus ,
    Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, pp.241-244, 2008.
  81. Masaki Hashizume, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu :
    Fault Analysis of Interconnect Opens in 90nm ICs with Device Simulator ,
    Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, pp.249-252, 2008.
  82. Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
    Test Method for DetectingOpen Leads of Low Voltage LSIs ,
    Proc. of ICEP2008, pp.457-462, 2008.
  83. Masao Takagi, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
    Applied AC Voltage for Detecting Open Leads of CMOS LSI by Monitoring Supply Current under AC Electric Field ,
    Journal of Japan Institute of Electronics Packaging, Vol.10, No.3, pp.219-228, 2007.(in Japanese)
  84. Ono Akira, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
    Open Lead Detection of CMOS Logic Circuits by Low Pressure Probing ,
    Proc. of ICEP2007, pp.359-364, 2007.
  85. Masaki Hashizume, Masahiro Ichimiya, Akira Ono and Hiroyuki Yotsuyanagi :
    Test Circuit for Vectorless Open Lead Detection of CMOS ICs ,
    IEEE 6-th International Board Test Workshop, 2007.
  86. Masaki Hashizume, Yuuki Ogata, Mitsuru Tojo, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
    Interconnect Open Detection by Supply Current Testing under AC Electric Field Application ,
    IEEE International Workshop on Current and Defect Based Testing, pp.25-29, 2007.
  87. Hiroyuki Yotsuyanagi, Takeshi Iihara and Masaki Hashizume :
    On SoC Testing Using Multiple Scan Chains with Scan Tree Configurations ,
    IEEE 8th Workshop on RTL and High Level Testing (WRTLT07), pp.151-156, 2007.
  88. Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi and Yukiya Miura :
    Current Testable Design of Resistor String DACs ,
    Proc. of IEEE 16th Asian Test Symposium, pp.399-403, 2007.
  89. Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines ,
    Proc. of IEEE 16th Asian Test Symposium, pp.39-44, 2007.
  90. Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines ,
    IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp.243-251, 2007.
  91. Ono Akira, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
    Open Lead Detection of CMOS Logic Circuits by Low Pressure Probing ,
    Proc. of ICEP2007, pp.359-364, 2007.
  92. Eiji Tasaka, Masaki Hashizume, Seiichi Nishimoto, Hiroyuki Yotsuyanagi, Takahiro Oie, Ikuro Morita and Toshihiro Kayahara :
    At Speed Testing of Bus Interconnects in Microcomputers ,
    IEEE 7th Workshop on RTL and High Level Testing (WRTLT06), pp.123-127, Fukuoka, Nov. 2006.
  93. Hiroyuki Yotsuyanagi, Tomohiko Nagashima and Masaki Hashizume :
    Test Time Reduction for Scan Circuits by Selection of a Flip-flop with Hold Operation ,
    7th Workshop on RTL and High Level Testing (WRTLT06), pp.81-85, Fukuoka, Nov. 2006.
  94. Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura :
    A BIC Sensor Capable of Adjusting IDDQ Limit in Tests ,
    Proc. of 15th Asian Test Symposium, pp.69-74, Fukuoka, Nov. 2006.
  95. Tojo Mitsuru, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
    Current Testing of Interconnect Opens between CMOS LSIs Having Scan Cells ,
    IEEE International Workshop on Current and Defect Based Testing, pp.39-42, Santa Clara, Oct. 2006.
  96. Masaki Hashizume and Hiroyuki Yotsuyanagi :
    Test Circuit for Open Lead Detection of CMOS ICs Based on Supply Current ,
    IEEE European Board Test Workshop, Southampton, UK, May 2006.
  97. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application ,
    Proc. of ICEP2006, pp.147-152, Tokyo, April 2006.
  98. Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
    Test Time Reduction Method for Scan Design with Clock-Control DFT ,
    Proc. of RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.441-444, Honolulu, March 2006.
  99. Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura :
    Current Testable Design of Registor String DACs ,
    IEEE International Workshop on Electronic Design, Test and Applications, pp.197-200, Kuala Lumpur, Malaysia, Jan. 2006.
  100. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita :
    Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees,
    Journal of Electronic Testing: Theory and Applications, Vol.21, No.6, pp.613-620, 2005.
  101. Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada :
    Statistical Supply Current Test Method for Opens in TTL Circuits with IC Characteristics Variations ,
    Journal of Japan Institute of Electronics Packaging, Vol.8, No.3, pp.199-207, 2005. (in Japanese)
  102. Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
    Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops ,
    IEEE 6th Workshop on RTL and High Level Testing (WRTLT05), pp.79-83, 2005.
  103. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing ,
    Proc. of IEEE International Symposium on Circuits and Systems, pp.2995-2998, 2005.
  104. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Vectorless Open Pin Detection Method for CMOS Logic Circuits ,
    Proc. of International Conference on Electronics Packaging, pp.391-396, 2005.
  105. Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara :
    Fail-Safe Evaluation Method for Boiler Control Circuits by Circuit Simulation ,
    Proc. of RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.395-398, Honolulu, March 2005.
  106. Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Electrical Detection of Pin Shorts by Supply Current of PIC ,
    Proc. of RISP International Workshop on Nonlinear Circuit and Signal Processing, pp.171-174, 2005.
  107. Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application ,
    Proc. of the ECWC 10 Conference, pp.P03-5-1-P03-5-5, 2005.
  108. Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto :
    Genetic State Reduction Method of Incompletely Specified Machines,
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, pp.1555-1563, 2004.
  109. Masao Takagi, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Lead Open Detection Based on Supply Current of CMOS LSIs ,
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, pp.1330-1337, 2004.
  110. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
    Test Sequence Generation for Test Time Reduction of IDDQ Testing ,
    IEICE Transactions on Information and Systems, Vol.E87-D, No.3, pp.537-543, 2004.
  111. Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits,
    IEICE Transactions on Information and Systems, Vol.E87-D, No.3, pp.571-579, 2004.
  112. Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita and Takeomi Tamesada :
    IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment ,
    Proc. of IEEE 13th Asian Test Symposium, pp.112-117, 2004.
  113. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application,
    Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems, pp.I-557-I-560, 2004.
  114. Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Tsukimoto Isao and Takeomi Tamesada :
    AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs ,
    Proc. of International Conference on Electronics Packaging, pp.217-222, 2004.
  115. Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits ,
    Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, pp.306-311, 2004.
  116. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita :
    On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure ,
    Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, pp.269-274, 2004.
  117. Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Practical Fault Coverage of Supply Current Tests for Bipolar ICs ,
    Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, pp.189-194, 2004.
  118. Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    CMOS Open Fault Detection by Appearance Time of Switching Supply Current ,
    Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, pp.183-188, 2004.
  119. Hiroyuki Yotsuyanagi, Taisuke Iwakiri, Masaki Hashizume and Takeomi Tamesada :
    Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field ,
    IEICE Transactions on Information and Systems, Vol.E86-D, No.12, pp.2666-2673, 2003.
  120. Masaki Hashizume, Eiji Tasaka, Hiroyuki Yotsuyanagi, Toshihiro Kayaharam Ikuro Morita and Takahiro Oie :
    A Supply Current Test Method for Bridging Faults in CMOS Microprocessor Based Circuits ,
    Journal of Japan Institute of Electronics Packaging, Vol.6, No.7, pp.564-572, 2003 (in Japanese)
  121. Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada :
    A Test CIrcuti for Pin Shorts Generating Oscillation in CMOS Logic CIrcuits ,
    IEICE Transactions on Information and Systems, Vol.J86-D-I, No.6, pp.402-411, 2003.(in Japanese)
  122. Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada :
    Pin Open Detection for CMOS Logic ICs by Measuring Supply Current under AC Electric Field ,
    Journal of Japan Institute of Electronics Packaging, Vol.6, No.2, pp.140-146, 2003. (in Japanese)
  123. Masaki Hashizume, Takeda Teppei, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura and Kozo Kinoshita :
    A BIST Circuit for IDDQ Tests ,
    Proc. of IEEE Twelfth Asian Test Symposium, pp.390-395, 2003.
  124. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita :
    Reducing Scan Shifts using Folding Scan Trees ,
    Proc. of IEEE Twelfth Asian Test Symposium, pp.6-11, 2003.
  125. Masaki Hashizume, Makoto Kawajiri, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Testability of Supply Current Test in an AGC Circuit ,
    Proc. of 2003 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, pp.836-839, 2003.
  126. Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Testability of Pin Open in Small Outline Package ICs by Supply Current Test ,
    Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications, pp.832-835, 2003.
  127. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    Electric Field Application Method Effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits ,
    Proc. of International Conference on Electronics Packaging, pp.75-80, 2003.
  128. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
    CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply ,
    IEICE Transactions on Information and Systems, Vol.E85-D, No.10, pp.1542-1550, 2002.
  129. Masaki Hashizume, Teppei Takeda, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura and Kozo Kinoshita :
    IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates ,
    IEICE Transactions on Information and Systems, Vol.E85-D, No.10, pp.1534-1541, 2002.
  130. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
    Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States ,
    IEICE Transactions on Information and Systems, Vol.E85-D, No.10, pp.1605-1608, 2002.
  131. Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto :
    Simplification of Incompletely Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism,
    IEEE 3rd Workshop on RTL and High Level Testing (WRTLT02), pp.74-78, 2002.
  132. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
    Test Time Reduction for IDDQ Testing by Arranging Test Vectors ,
    Proc. of IEEE Eleventh Asian Test Symposium, pp.423-428, 2002.
  133. M.Hashizume,N.Inou,H.Yotsuyanagi,T.Tamesada :
    Oscillation Frequency Estimation for Detecting Feedback Bridging Faults,
    Proc. of 2002 International Technical Conference on Circuits/Systems, Computers and Communications,Vol.3,pp.1980-1983,July 2002.
  134. I.Tsukimoto,M.Hashizume,Y.Mushiaki,H.Yotsuyanagi,T.Tamesada :
    Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits,
    Proc. of 2002 International Technical Conference on Circuits/Systems, Computers and Communications,Vol.3,pp.1972-1975,July 2002.
  135. M.Hashizume,E.Tasaka, M.Ichimiya, H.Yotsuyanagi,T.Tamesada, T.Kayahara :
    Power-off Vectorless Test Method for Pin Opens in CMOS Logic Circuits,
    Proc. of Electronics Packaging, pp.363-368,April 2002.
  136. M.Hashizume,M.Ichimiya,H.Yotsuyanagi,T.Tamesada :
    Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits,
    Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications,pp.459-461,Jan. 2002.
  137. M.Hashizume,M.Sato,H.Yotsuyanagi,T.Tamesada :
    Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits,
    Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications,pp.459-461,Jan. 2002.
  138. H.Yotsuyanagi,M.Hashizume,T.Iwakiri,M.Ichimiya,T.Tamesada :
    Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field,
    Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications,pp.387-391,Jan. 2002.
  139. M.Hashizume,M.Ichimiya,H.Yotsuyanagi,T.Tamesada :
    CMOS Open Defect Detection Based on Supply Current in Time-variable Electric Field and Supply Voltage Application,
    Proc. of Tenth Asian Test Symposium,pp.117-122,Nov. 2001.
  140. T.Takeda,M.Hashizume,M.Ichimiya,H.Yotsuyanagi,Y.Miura,K.Kinoshita :
    IDDQ Sensing Technique for High Speed IDDQ Testing,
    Proc. of Tenth Asian Test Symposium,pp.111-116,Nov. 2001
  141. H.Yotsuyanagi,S.Hata,M.Hashizume,T.Tamesada :
    Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States,
    Proc. of Tenth Asian Test Symposium,pp.23-28,Nov. 2001.
  142. H.Yotsuyanagi,M.Hashizume,T.Iwakiri,M.Ichimiya,T.Tamesada :
    Test Pattern for Supply Current Test of Open Defects by Applying Time-variable Electric Field,
    Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,pp.287-295,Oct. 2001.
  143. T.Takeda,M.Hashizume,M.Ichimiya,H.Yotsuyanagi,T.Tamesada :
    A High Speed IDDQ Sensor Circuit,
    Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications,Vol.2,pp.438-441,July 2001.
  144. T.Koyama,M.Hashizume,T.Arakawa,M.Ono :
    Efficient Test Methods for CMOS SRAMs with Quiescent Write Supply Current,
    Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications,Vol.1,pp.434-437,July 2001.
  145. M.Hashizume,E.Tasaka,H.Yotsuyanagi,T.Tamesada,T.Kayahara :
    Fault Simulator for Test Program Generation in Supply Current Tests of Microprocessor Based Boiler Control Circuits,
    Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications,Vol.1,pp.446-449,July 2001.
  146. A.Tsuji,M.Hashizume,M.Ichimiya,H.Yotsuyanagi,T.Tamesada :
    Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field,
    Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications,Vol.1,pp.438-441,July 2001.
  147. M.Hashizume,H.Hoshika,H.Yotsuyanagi,T.Tamesada :
    Testable Static CMOS PLA for IDDQ Testing,
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,Vol.E84-A,No.6,pp.1488-1495,2001.
  148. M.Hashizume,M.Ichimiya, A.Tsuji,H.Yotsuyanagi,T.Tamesada :
    Supply Current Test for Pin Opens in CMOS Logic Circuits,
    Proc. of Electronics Packaging, pp.363-368,April 2001.
  149. M.Hashizume, M.Ichimiya, H.Yotsuyanagi and T.Tamesada :
    CMOS Open Defect Detection by Supply Current Test,
    DATE 2001, pp.509-513, Mar. 2001.
  150. M.Hashizume, H.Yotsuyanagi, M.Ichimiya, T.Tamesada and M.Takeda :
    High Speed IDDQ Test and Its Testability for Process Variation,
    Proc. of IEEE Asian Test Symposium, pp.344-349, 2000.
  151. M.Hashizume, H.Yotsuyanagi, T.Tamesada and M.Takeda :
    Testable Analysis of IDDQ Testing with Large Threshold Value,
    IEEE Internatinal Symposium on Defect and Fault Tolerance in VLSI Systems, pp.367-375, 2000.
  152. H.Yotsuyanagi, M.Hashizume and T.Tamesada :
    Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables,
    Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.355-358, 2000.
  153. S.Yamamoto, M.Hashizume, H.Yotsuyanagi and T.Tamesada :
    Oscillation Frequency Estimation of Feedback Bridging Faults for Test Circuit Design,
    Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.343-346, 2000.
  154. H.Hoshika, M.Hashizume, H.Yotsuyanagi and T.Tamesada :
    IDDQ Testable Design of Static CMOS PLAs with Low Power Consumption,
    Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.351-354, 2000.
  155. T.Ohnishi, H.Yotsuyanagi, M.Hashizume and T.Tamesada :
    A Test Input Sequence for Test Time Reduction of IDDQ Testing,
    Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.367-370, 2000.
  156. Y.Mushiaki, M.Hashizume, H.Yotsuyanagi and T.Tamesada :
    Practical Fault Coverage of Supply Current Testing for Open Fault in TTL Combinational Circuits,
    Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.383-386, 2000.
  157. M.Sato, M.Hashizume, H.Yotsuyanagi and T.Tamesada :
    Power Supply Circuits with Small Size for Adiabatic Dynamic CMOS Logic Circuits,
    Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, pp.179-182, 2000.
  158. H.Yotsuyanagi, M.Hashizume and T.Tamesada :
    Adding Transitions of Undefined States to State Transition Tables for Testability Enhancement,
    IEEE Workshop on RTL ATPG & DFT (WRTLT00), 2000.
  159. M.Hashizume,H.Hoshika,H.Yotsuyanagi,T.Tamkesada :
    IDDQ Testable Design of Static CMOS PLAs,
    Proc. of the IEEE International Workshop on Defect Based Testing, pp.70-75, 2000
  160. M.Hashizume,S.Yamamoto,H.Yotsuyanagi,T.Tamesada:
    Identification of Feedback Bridging Faults with Oscillation,
    Proc. of the IEEE 8-th Asian Test Symposium,pp.25-30,1999
  161. M.Hashizume,H.Yotsuyanagi,T.Tamesada,E.Tasaka,T.Kayahara:
    Supply Current Testing for Bridging Faults in Microprocessor Based Sequence Control Circuits,
    Proc. of the 8-th Electronic CircuitsWorld Convention,pp.T2-3-1-T2-3-7, 1999.
  162. M.Hashizume,T.Tamesada,T.Koyama,AJ van de Goor :
    Logical Fault Detection Based on Supply Current in Write Operation of CMOS SRAM ICs,
    Trans. on IEIECE,Vol.J82-D-I,No.7,pp.906-915,1999.(in Japanease)
  163. M.Hashizume, M.Sato,H.Yotsuyanagi,T.Tamesada :
    Power Supply Circuit for Adiabatic Dynamic CMOS Logic Circuits,
    Proc. of 1999 International Techinical Conference on Circuits/Systems, Computers and Communications,pp162-165, 1999.
  164. M.Hashizume, T.Matsushima,T.Tamesada, T.Shimamoto, A.Sakamoto :
    State Reduction of Incompletely Specified Machines Based on Genetic Approach,
    Proc. of 1999 International Techinical Conference on Circuits/Systems, Computers and Communications,pp.888-891, 1999
  165. M.Hashizume, Y.Miura,M.Ichimiya,T.Tamesada, K.Kinoshita :
    A High Speed IDDQ Sensor for Low Voltage ICs,
    Proc. of the IEEE Seventh Asian Test Symposium,pp.327-331, 1998
  166. M.Hashizume,T.Tamesada,T.Shimamoto,A.Sakamot :
    Heuristic State Reduction Methods of Incompletely Specified Machines Proceding to Satisfy Covering Condition,
    IEICE Trans.Fundamentals,Vol.E81-A,No.6,pp.1045-1054, 1998.
  167. T.Kuchi,M.Hashizume, T.Tamesada :
    Test Input Generation for Supply Current Testing of Bridging Faults in Bipolar Combinational Logic Circuits,
    Proc. of IEEE International Workshop on IDDQ Testing,pp.14-18, 1998
  168. M.Hashizume,T.Tamesada,T.Koyama,,A.J.van de Goor :
    CMOS SRAM Functional Test with Quiescent Write Supply Current,
    Proc. of IEEE International Workshop on IDDQ Testing,pp.4-8, 1998.
  169. T.Kuchii,M.Hashizume,T.Tamesada :
    Current Testing of Open Faults in TTL Combinational Circuits on Printes Circuit Boards,
    Journal of Japan Institute of Electronics Packaging ,Vol.1,No.4,pp.284-293,1998
  170. M.Hashizume, T.Kuchii, T.Tamesada :
    Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates,
    Proc. of the IEEE Sixth Asian Test Symposium,pp.372-377, 1997
  171. M.Hashizume, M.Ichimiya, T.Tamesada :
    A Current Sensing Circuit for Feedback Bridging Faults,
    Proc. of the IEEE International Workshop on IDDQ Testing,pp.110-113, 1997.
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